<html><body><samp><pre>
<!@TC:1731498066>
# Wed Nov 13 19:41:05 2024


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03L-SP1
Install: D:\lscc\diamond\3.13\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-HUAWEI

Implementation : MXO2_2000HC
<a name=mapperReport23></a>Synopsys Lattice Technology Pre-mapping, Version map202303lat, Build 132R, Built Aug 31 2023 04:16:35, @</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 123MB)


Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 137MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1731498066> | No constraint file specified. 
Linked File:  <a href="E:\My_Designs\2024\Laser_Device_Project\1064_CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC_scck.rpt:@XP_FILE">CL202_MXO2_2000HC_scck.rpt</a>
See clock summary report "E:\My_Designs\2024\Laser_Device_Project\1064_CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC_scck.rpt"
@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1731498066> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1731498066> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1731498066> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 137MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 137MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)

NConnInternalConnection caching is on
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1731498066> | Applying initial value "000000000000000000000000" on instance LockData[23:0]. 
<font color=#A52A2A>@W:<a href="@W:FX474:@XP_HELP">FX474</a> : <!@TM:1731498066> | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. </font> 

Starting HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)


Finished HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)


Started DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)


Finished DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 197MB)


Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 198MB)


mixed edge conversion for GCC is OFF
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1731498066> | GCC encountered Inferred Clock constraint on net GCC considers to be data U3.Clk_10ms[17]; this will likely lead to failure to convert</font> 
@N:<a href="@N:MF578:@XP_HELP">MF578</a> : <!@TM:1731498066> | Incompatible asynchronous control logic preventing generated clock conversion. 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1731498066> | GCC encountered Inferred Clock constraint on net GCC considers to be data U3.PulseOut; this will likely lead to failure to convert</font> 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1731498066> | GCC encountered Inferred Clock constraint on net GCC considers to be data Clk_Count[16]; this will likely lead to failure to convert</font> 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1731498066> | GCC encountered Inferred Clock constraint on net GCC considers to be data Clk_Count[13]; this will likely lead to failure to convert</font> 

Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 198MB)

<font color=#A52A2A>@W:<a href="@W:BZ101:@XP_HELP">BZ101</a> : <!@TM:1731498066> | Potential glitch can occur at the output of 1 instances  </font> 

Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 199MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 199MB)

@N:<a href="@N:FX1184:@XP_HELP">FX1184</a> : <!@TM:1731498066> | Applying syn_allowed_resources blockrams=7 on top level netlist Top  

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 199MB)



<a name=mapperReport24></a>Clock Summary</a>
******************

          Start                                       Requested     Requested     Clock                      Clock          Clock
Level     Clock                                       Frequency     Period        Type                       Group          Load 
---------------------------------------------------------------------------------------------------------------------------------
0 -       Top|Clk                                     100.0 MHz     10.000        inferred                   (multiple)     197  
1 .         Top|Clk_Count_derived_clock[13]           100.0 MHz     10.000        derived (from Top|Clk)     (multiple)     16   
1 .         LaserPulse|Clk_10ms_derived_clock[17]     100.0 MHz     10.000        derived (from Top|Clk)     (multiple)     9    
1 .         Top|Clk_Count_derived_clock[16]           100.0 MHz     10.000        derived (from Top|Clk)     (multiple)     9    
                                                                                                                                 
0 -       Top|FSMC_NWE                                100.0 MHz     10.000        inferred                   (multiple)     99   
                                                                                                                                 
0 -       Top|FSMC_NADV                               100.0 MHz     10.000        inferred                   (multiple)     16   
                                                                                                                                 
0 -       LaserPulse|PulseOut_inferred_clock          100.0 MHz     10.000        inferred                   (multiple)     0    
=================================================================================================================================



Clock Load Summary
***********************

                                          Clock     Source                             Clock Pin              Non-clock Pin            Non-clock Pin   
Clock                                     Load      Pin                                Seq Example            Seq Example              Comb Example    
-------------------------------------------------------------------------------------------------------------------------------------------------------
Top|Clk                                   197       Clk(port)                          Clr_Count[22:0].C      -                        -               
Top|Clk_Count_derived_clock[13]           16        Clk_Count[16:0].Q[13](dff)         U2.Count[7:0].C        -                        -               
LaserPulse|Clk_10ms_derived_clock[17]     9         U3.Clk_10ms[17:0].Q[17](sdffr)     U3.Stop_sig.C          -                        -               
Top|Clk_Count_derived_clock[16]           9         Clk_Count[16:0].Q[16](dff)         TB_watchdog[8:0].C     -                        -               
                                                                                                                                                       
Top|FSMC_NWE                              99        FSMC_NWE(port)                     reg_mem[15:0].CLK      -                        -               
                                                                                                                                                       
Top|FSMC_NADV                             16        FSMC_NADV(port)                    FSMC_Add[15:0].C       -                        -               
                                                                                                                                                       
LaserPulse|PulseOut_inferred_clock        0         U3.PulseOut.OUT(and)               -                      U6.count_set[15:0].E     TB_sig.B[0](mux)
=======================================================================================================================================================

<font color=#A52A2A>@W:<a href="@W:MT531:@XP_HELP">MT531</a> : <a href="e:\my_designs\2024\laser_device_project\1064_cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:367:2:367:4:@W:MT531:@XP_MSG">cl202_mxo2-2000hc_top.vhd(367)</a><!@TM:1731498066> | Found signal identified as System clock which controls 17 sequential elements including SPulseCount[15:0].  Using this clock, which has no specified timing constraint, can prevent conversion of gated or generated clocks and can adversely impact design performance. </font>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="e:\my_designs\2024\laser_device_project\1064_cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:594:2:594:4:@W:MT529:@XP_MSG">cl202_mxo2-2000hc_top.vhd(594)</a><!@TM:1731498066> | Found inferred clock Top|Clk which controls 197 sequential elements including U4.Clk_Count[6:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="e:\my_designs\2024\laser_device_project\1064_cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:131:7:131:16:@W:MT529:@XP_MSG">cl202_mxo2-2000hc_top.vhd(131)</a><!@TM:1731498066> | Found inferred clock Top|FSMC_NWE which controls 99 sequential elements including reg_mem_5[15:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="e:\my_designs\2024\laser_device_project\1064_cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:241:2:241:4:@W:MT529:@XP_MSG">cl202_mxo2-2000hc_top.vhd(241)</a><!@TM:1731498066> | Found inferred clock Top|FSMC_NADV which controls 16 sequential elements including FSMC_Add[15:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



<a name=clockReport25></a>#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[</a>

3 non-gated/non-generated clock tree(s) driving 297 clock pin(s) of sequential element(s)
4 gated/generated clock tree(s) driving 51 clock pin(s) of sequential element(s)
0 instances converted, 51 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
<a href="@|L:E:\My_Designs\2024\Laser_Device_Project\1064_CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:Clk@|E:Clk_Count[16:0]@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0 @XP_NAMES_BY_PROP">ClockId_0_0</a>       Clk                 port                   197        Clk_Count[16:0]
<a href="@|L:E:\My_Designs\2024\Laser_Device_Project\1064_CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:FSMC_NADV@|E:FSMC_Add[15:0]@|F:@syn_dgcc_clockid0_6==1@|M:ClockId_0_6 @XP_NAMES_BY_PROP">ClockId_0_6</a>       FSMC_NADV           port                   16         FSMC_Add[15:0] 
<a href="@|L:E:\My_Designs\2024\Laser_Device_Project\1064_CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:FSMC_NWE@|E:reg_mem_5[15:0]@|F:@syn_dgcc_clockid0_7==1@|M:ClockId_0_7 @XP_NAMES_BY_PROP">ClockId_0_7</a>       FSMC_NWE            port                   84         reg_mem_5[15:0]
=======================================================================================
================================================================== Gated/Generated Clocks ===================================================================
Clock Tree ID     Driving Element             Drive Element Type     Unconverted Fanout     Sample Instance        Explanation                               
-------------------------------------------------------------------------------------------------------------------------------------------------------------
<a href="@|L:E:\My_Designs\2024\Laser_Device_Project\1064_CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:U3.Clk_10ms[17:0].Q[17]@|E:U3.Count_stop[7:0]@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1 @XP_NAMES_BY_PROP">ClockId_0_1</a>       U3.Clk_10ms[17:0].Q[17]     sdffr                  9                      U3.Count_stop[7:0]     Derived clock on input (not legal for GCC)
<a href="@|L:E:\My_Designs\2024\Laser_Device_Project\1064_CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:Clk_Count[16:0].Q[13]@|E:U2.Count[7:0]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3 @XP_NAMES_BY_PROP">ClockId_0_3</a>       Clk_Count[16:0].Q[13]       dff                    16                     U2.Count[7:0]          Derived clock on input (not legal for GCC)
<a href="@|L:E:\My_Designs\2024\Laser_Device_Project\1064_CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:U3.PulseOut.OUT@|E:SPulseCount[15:0]@|F:@syn_dgcc_clockid0_5==1@|M:ClockId_0_5 @XP_NAMES_BY_PROP">ClockId_0_5</a>       U3.PulseOut.OUT             and                    17                     SPulseCount[15:0]      Clock source is invalid for GCC           
<a href="@|L:E:\My_Designs\2024\Laser_Device_Project\1064_CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:Clk_Count[16:0].Q[16]@|E:TB_watchdog[8:0]@|F:@syn_dgcc_clockid0_8==1@|M:ClockId_0_8 @XP_NAMES_BY_PROP">ClockId_0_8</a>       Clk_Count[16:0].Q[16]       dff                    9                      TB_watchdog[8:0]       Derived clock on input (not legal for GCC)
=============================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######


Summary of user generated gated clocks:
0 user generated gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)

@N:<a href="@N:FX1143:@XP_HELP">FX1143</a> : <!@TM:1731498066> | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 199MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 200MB)


Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 200MB peak: 200MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 115MB peak: 201MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Nov 13 19:41:06 2024

###########################################################]

</pre></samp></body></html>
